In many high density electronic device manufacturing processes, semiconductor integrated circuit chips are bonded to a substrate by a solder reflow process. In the prior art (as illustrated in FIGS. 1 and 2) a surface mountable package such as a microelectronic device package 10, a semiconductor integrated circuit chip or the like is operatively joined to a substrate, printed circuit board or other device 12 after the solder reflow process has been completed. The interconnection material between the microelectronic device package 10 and the substrate or device 12 is in the form of a solder bump, drop, ball or deposit 14 prior to the solder reflow process. The solder bumps or drops 14 are placed on wettable metal pads 16 of the microelectronic device 10 by one of various processes which include (1) deposition through a mask plus solder reflow, (2) electroplating plus solder reflow and (3) pick-and-place of the solder bumps, etc.
The actual bonding processes utilize solder bumps or balls deposited on the wettable metal pads 16 on the microelectronic device 10. Microelectronic device 10 (the upside-down chip or "flip chip") is then flipped over (see FIG. 2) and the solder bumps 14 aligned with the correct matching footprint of solder-wettable terminals, contact pads or bond pads 18 on the substrate 12. Heat is then applied and all joints or interconnections between the wettable metal pads 16 on the microelectronic device 10 and the solder-wettable terminals, contact pads or bond pads 18 on the substrate 12 are made simultaneously by reflowing the solder in the solder bumps or drops 14. Typically, such interconnections are made with solder bumps 14 which are about 100 to 150 .mu.m (microns) in diameter with several hundred to several thousand solder bumps per chip. Manufacturing processes, however, are moving toward more interconnections per chip and thus require smaller solder bumps since the interconnections are closer together.
With regard to prior art methods of depositing solder through a mask plus reflow for creating solder bumps, the disadvantages include the high overall cost of the process. Furthermore, the quality and repeatability of the solder alloy is not good and the masks get coated with the solder materials and must be continuously cleaned or replaced.
With regard to the prior art method of depositing solder by electroplating plus reflow, the disadvantages of this process include high overall cost because of the photolithography process. Furthermore, the solder-plating step presents environmental waste treatment problems and solder alloys are not consistent and usually contain impurities.
With regard to the prior art method of depositing solder using the pick-and-place of solder bumps, the disadvantages of this process include high cost of the equipment needed. Furthermore, the process is not suitable for volume production and there is danger to individuals in the handling and controlling of the small solder balls.
For high density integrated circuit interconnections using flip-chip bonding, the major failure mechanism is failure of the solder bumps due to thermal expansion stress. The present invention provides an interconnection array which greatly reduces thermal expansion stress for a given thermal expansion mismatch between the high density integrated circuit chip and the substrate.